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VP310 satellite channel decoder preliminary information shortform technical manual ds 5155 -1.00 21/04/99 ordering information VP310 - key features VP310 cg gq1r conforms to ebu specification for dvb-s and directv specification for dss. on-chip digital filtering supports 1 to 45mbaud symbol rates. on-chip 6-bit 60 or 90mhz dual-adc. high speed scanning mode for blind symbol rate and code rate acquisition. up to 15mhz lnb frequency tracking. fully digital timing and phase recovery loops. high level software interface for minimum development time. diseqc? v1.1: control outputs for full control of lnb and dish. applications dvb 1 to 45mbaud compliant sate llite receivers. dss 20mbaud compliant sate llite receivers. scpc receivers. (single channel per carrier) smatv trans-modulators. (single master antenna tv) lmds. (local multipoint distribution service) satellite pc applications. the VP310 is a qpsk/bpsk 1 to 45mbaud demodulator and channel decoder for digital satellite television transmissions to the eur opean broadcast union ets 300 421 specification. it receives analog i and q signals from the tuner, digitises and digitally demodulates this signal, and implements the complete dvb/dss fec (forward error correction), and de-scrambling function. the output is in the form of mpeg2 or dss transport stream data packets. the VP310 also provides automatic gain control to the rf front-end devices. the VP310 has a serial i2c port interface to the control microprocessor. minimal software is required to control the VP310 because of the built in automatic search and decode control functions.
VP310 preliminary data 2 overview the VP310 is a qpsk/bpsk 1 to 45mbaud demodulator and channel decoder for digital satellite television transmissions compliant to both dvb-s and dss standards and other systems, such as lmds, that use the same architecture. a command driven control ( cdc) system is provi ded making the VP310 very simple to program. after the tuner has been programmed to the required frequency, to acquire a dvb transmission, the VP310 requires a minimum of five registers to be written, see figure 15 on page 19. activity flow diagrams for initialisation and basic channel change are included in section 2. the VP310 provides a monitor of bit error rate after the qpsk module and also after the viterbi module. for receiver installation, a high speed scan or blind search mode is available. this allows all signals from a given sate llite to be evaluated for fr equency, symbol rate and convolutional coding scheme. dual adc timin g recover y matched filter phase recover y i2c interface dvb dss fec analo g agc control acquisition control clock generation mpeg/ dss packets bus i/o q i/p i i/p de-rotator decimation filteriin g figure 1. VP310 functional block diagram.
VP310 preliminary data 3 additional features i2c bus microprocessor interface. all digital clock and carrier recovery. on-chip pll clock generation using low cost 10 to 15mhz crystal. 3.3v operation. 80 pin mqfp package. low external component count. commercial temperature range 0 to 70c. demodulator bpsk or qpsk programmable. optional fast acquisition mode for low symbol rates. viterbi programmable decoder rates 1/2, 2/3, 3/4, 5/6, 6/7, 7/8. constraint length k=7. trace back depth 128. extensive snr and ber monitors. de-interleaver compliant with dvb and dss standards. reed solomon (204, 188) for dvb and (146,130) for dss. reed solomon bit-error-rate monitor to indicate viterbi performance. de-scrambler ebu specification de-scrambler for dvb mode. outputs mpeg transport parallel & serial output. integrated mpeg2 tei bit processing for dvb only. application support channel decoder system evaluation board. i2c interface board to pc. windows based evaluation software. ansi c generic software. application support help desk via email/telephone.
VP310 preliminary data 4 please note: this manual has the following convention: all numerical values are s hown as decimal numb ers, unless otherwise defined. 1. functional description 1.1 introduction VP310 is a single-chip variable rate digital qpsk/bpsk sate llite dem odulator and channel decoder. the VP310 accepts base-band in-phase and quadrature analog signals and delivers an mpeg or dss packet data stream. digital filtering in VP310 removes the need for any external anti-alias filtering for all symbol rates from 1 to 45mbaud. frequency, timing and carrier phase recovery are all digital and the only feed-back to the analog front-end is for automatic gain control. the digital phase recovery loop enables very fine bandwidth control that is needed to overcome performance degradation due to phase and thermal noise. all acquisition algorithms are built into the VP310 controller. the VP310 can be operated in a command driven control (cdc) mode by specifying the symbol rate and viterbi code rate. there is also a provision for a search for unknown symbol rates and viterbi code rates. 1.2 analog-to-digital converter the VP310 contains dual 6-bit a/d converters which each sample a 1.0vpp single-ended analog input at up to 90mhz. the fixed rate sampling clock is provided on-chip using a programmable pll needing only a low cost 10 to 15mhz crystal. different crystal frequencies can be combined with different pll ratios, depending on the maximum symbol rate, allowing a flexible approach to clock generation. 1.3 qpsk demodulator the demodulator in the VP310 consists of signal amplitude offset compensation, frequency offset compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering. the decimation filters give continuous operation from 2mbits/s to 90mbits/s allowing one receiver to cover the needs of the consumer market as well as the single carrier per channel (scpc) market with the same components without compromising performance, that is, the channel reception is within 0.5db from theory. for a given symbol rate, control algorithms on the chip detect the number of decimation stages needed and switch them in automatically. the frequency offset compensation circuitry is capable of tracking out up to 15mhz frequency offset. this allows the system to cope with relatively large frequency uncertainties introduced by the low noise block (lnb). full control of the lnb is provided by the diseqc outputs from the VP310. horizontal / vertical polarisation and an instruction modulated 22khz signal are available under register control. all diseqc v1.1 functions are implemented on the VP310.
VP310 preliminary data 5 an internal state machine that handles all the demodulator functions controls the signal tracking and acquisition. various pre-set modes are available as well as blind acquisition where the receiver has no prior knowledge of the received signal. fast acquisition algorithms have been provided for low symbol rate applications. full interactive control of the acquisition function is possible for debug purposes. in the event of a signal fade or a cycle slip, qpsk demodulator allows sufficient time for the fec to re-acquire lock, for example, via a phase rotation in the viterbi decoder. this is to minimise the loss of signal due to the signal fade. only if the fec fails to re-acquire lock for a long period (which is programmable) would qpsk try to re-acquire the signal. the matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with dss and dvb standards. although not a part of the dvb standard, VP310 allows a roll-off of 0.20 to be used with other dvb parameters. an agc signal is provided to control the signal levels in the tuner section of the receiver and ensure the signal level fed to the VP310 is set at an optimal value under all reception conditions. the VP310 provides comprehensive information on the input signal and the state of the various parts of the device. this information includes signal to noise ratio (snr), signal level, agc lock, timing and carrier lock signals. a maskable interrupt output is available to inform the host controller when events occur. 1.4 forward error correction the VP310 contains fec blocks to enable error correction for dvb-s and dss transmissions. the viterbi decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8. the block features automatic synchronisation and automatic code rate detection. the trace back depth of 128 provides better performance at high code rates and the built-in synchronisation algorithm allows the viterbi decoder to lock onto signals with very poor signal-to-noise ratios. viterbi bit error rate monitor provides an indication of the error rate at qpsk output. the 24-bit error count register in the viterbi decoder allows the bit error rate at the output of the qpsk demodulator to be monitored. the 24-bit bit error count register in the reed-solomon decoder allows the viterbi output bit error rate to be monitored. the 16-bit uncorrectable packet counter yields information about the output packet error rate. these three monitors and the qpsk snr register allows the performance of the device and its individual components, such as the qpsk demodulator and the viterbi decoder, to be monitored extensively by the external microprocessor. the frame/byte align block features a sophisticated synchronisation algorithm to ensure reliable recovery of dvb and dss framed data streams under worst case signal conditions. the de- interleaver uses on-chip ram and is compatible with the dvb and dss algorithms. the reed-solomon decoder is a truncated version of the (255, 239) code. the code block size is 204 for dvb and 146 for dss. the decoder provides a count of the number of uncorrectable blocks as well as the number of bit errors corrected. the latter gives an indication of the bit error rate at the output of the viterbi decoder .
VP310 preliminary data 6 in dvb mode, spectrum de-scrambling is performed compatible with the dvb specification. the final output is a parallel or serial transport data stream; packet sync; data clock; and a block error signal. the data clock may be inverted under software control. 1.4.1.1 viterbi error count measurement a method of estimating the bit error rate at the output of the qpsk block has been provided in the viterbi decoder. the incoming data bit stream is delayed and compared with the re-encoded and punctured version of the decoded bit stream to obtain a count of errors see figure 2 below. viterbi decoder delay comp error count data bit stream viterbi encoder figure 2. viterbi block diagram. the measurement system has a programmable register to determine the number of data bits (the error count period) over which the count is being recorded. a read register indicates the error count result and an interrupt can be generated to inform the host microprocessor that a new count is available. the vit_errper h-m-l group of three registers is programmed with required number of data bits (the error count period) (vit_errper[23:0]). the actual value is four times vit_errper[23:0]. the count of errors found during this period is loaded by the VP310 into the vit_errcnt h-m-l trio of registers when the bit count vit_errper[23:0] is reached. at the same time an interrupt is generated on the irq line. setting the ie_fec[2] bit in the ie_fec register enables the interrupt. reading the register does not clear vit_errcnt [23:0], it is only loaded with the error count.
VP310 preliminary data 7 vit_errper[23:0] data bits error count vit_errcnt[23:0] 0 0 irq figure 3. viterbi error count measurement. figure 3 above shows the bit errors rising until the maximum programmed value of vit_errper[23:0] is reached, when an interrupt is generated on the irq line to advise the host microprocessor that a new value of bit error count has been loaded into the vit_errcnt[23:0] register. the irq line will go high when the ie_fec register is read by the host microprocessor. vit_errcnt[23:0] vit_errper[23:0] the error count may be expressed as a ratio: vit_errcnt[23:0] vit_errper[23:0] * 4 1.4.1.2 viterbi error count coarse indication to assist in the process of aligning the receiver dish aerial, a coarse indication of the number of bit errors being received can be provided by monitoring the status line with the following set up conditions. the frequency of the output waveform will be a function of the bit error c ount (triggering the maximum value programmed into the vit_maxerr[7:0] register and the dish alignment on the satellite. this vit_m axerr mode is enabled by setting the fec_stat_en register bit b0. figure 4 on page 8 shows the bit errors rising to the maximum value programmed and triggering a change of state on the status line. the output signal w ill be in the audio frequency range.
VP310 preliminary data 8 status viterbi course bit error count vit_maxerr[7:0] 0 0 data bits figure 4. viterbi error count coarse indication. 1.4.2 the frame alignment block the frame alignment algorithm detects a sequence of correctly spaced synchronising bytes in the viterbi decoded bit-stream and arranges the input into blocks of data bytes. each block consists of 204 bytes for dvb and 147 bytes for dss. in the dss mode, the synchronising byte is removed from the data stream, so only 146 bytes of a block are passed to the next stage. the frame alignment block also removes the 180 phase ambiguity not removed by viterbi decoder. 1.4.3 the de-interleaver block 1.4.3.1 dvb before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve. this ensures the bytes are spaced out to avoid the possibility of a noise spike corrupting a group of consecutive message bytes. the diagram below shows conceptually how the convolutional de- interleaving system works. the synchronisation byte is always loaded into the first-in-first-out (fifo) memory in branch 0. the switch is operated at regular byte intervals to insert successively received bytes into successive branches. after 12 bytes have been received, byte 13 is written next to the synchronisation byte in branch 0, etc. in the VP310, this de-interleaving function is realised using on-chip random access memory (ram).
VP310 preliminary data 9 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 sync word route 17x1 17x2 bytes 17x3 bytes 17x4 bytes 17x5 bytes 17x6 bytes 17x7 bytes 17x8 bytes 17x9 bytes 17x10 bytes 17x11 bytes one byte per position figure 5. dvb conceptual diagram of the convolutional de-interleaver block . 1.4.3.2 dss before transmission, the data bytes are interleaved with each other in a cyclic pattern of thirteen. this ensures the bytes are spaced out to avoid the possibility of a noise spike corrupting a group of consecutive message bytes. the diagram below shows conceptually how the convolutional de- interleaving system works. on the VP310, this function is realised in the same random access memory (ram) as used for dvb, but utilising different addressing algorithm. 12d 12d 12d 0 1 output 145 input 2 figure 6. dss conceptual diagram of the convolutional de-interleaver block.
VP310 preliminary data 10 1.4.4 the reed solomon decoder block dvb and dss data are encoded using shortened versions of the reed-solomon code of block length 255, containing 239 message bytes and 16 check bytes, that is (255,239) with t = 8. both encoders use the same generator polynomial. the code block size for dvb is 204 and that for dss is 146. hence dvb code is (204, 188) and dss code is (146, 130), with both having t = 8. the block structure of the dvb and dss reed-solomon codes are as shown in figure 7 and figure 8 on page 10. the reed-solomon decoder can correct up to eight byte errors per packet. if there are more than 8 bytes containing errors, the packet is flagged as uncorrectable using the pin bkerr. in the case of dvb the transport error indicator (tei) bit of the mpeg packet is set to 1, if setting of tei is enabled. sync byte 187 bytes sync byte 187 bytes 16 check bytes reed solomon encoded block mpeg transport packet figure 7. dvb block structure. 130 bytes 130 bytes 16 check bytes reed solomon encoded block dss transport packet figure 8. dss block structure.
VP310 preliminary data 11 1.4.5 the energy dispersal (de-scrambler) block, dvb only before reed solomon encoding in the dvb transmission system, the mpeg2 data stream is randomised using the configuration shown in figure 9 below. this is a pseudo random binary sequence (prbs) generator, with the polynomial: 1 + x 14 + x 15 the prbs registers are loaded with the initialisation sequence as shown, at the start of the first transport packet in a group of eight packets. this point is indicated by the inverted sync byte b8 hex . the normal dvb sync byte is 47 hex . the data starting with the first byte after the sync byte is randomised by exclusive-oring data bits with the prbs. (the sync bytes themselves are not randomised). in the decoder, the process of de-randomising or de-scrambling the data is exactly the same as described above. the de-scrambler also inverts the sync byte b8hex so that all mpeg output packets have the same synch byte 47hex. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 100101010000000 initialisation sequence xor figure 9. dvb energy dispersal conceptual diagram. 1.4.6 output stage transport stream can be output in a byte-serial or bit-serial mode. the output interface consists of an 8-bit output, output clock, a packet validation level, a packet start pulse and a block error indicator. the output clock rate depends on the symbol rate, qpsk/bpsk choice, convolutional (viterbi) coding rate, dvb/dss choice and byte-parallel or bit-serial output mode. this rate is computed by VP310 to be very close to the minimum required to output packet data without packet overlap. furthermore, the packets at the output of VP310 are as evenly spaced as possible to minimise packet position movement in the transport layer. the maximum movement in the packet synchronisation byte position is limited to one output clock period.
VP310 preliminary data 12 1.5 control automatic symbol rate search, code rate search, signal acquisition and signal tracking algorithms are built into the VP310 using a sophisticated on-chip controller. the software interaction with the device is via a simple command driven control (cdc) interface. this cdc maps high level inputs such as symbol rates in mbaud and frequencies in mhz, to low level on- chip register settings. the on-chip control state machine and the cdc significantly reduces the software overhead as well as the channel search times. there is also an option for the host processor to by-pass both the cdc as well as the on-chip controller and take direct control of the qpsk demodulator. command driven control high level input/output (mbaud, mhz) VP310 format registers acquistion/ track state machine qpsk low level register read/write figure 10. VP310 control structure. once the VP310 has locked up, any frequency offset can be read from the lnb_freq error registers 7 and 8. the frequency synthesiser under the software control can be re-tuned in frequency to optimise the received signal within the saw bandwidth. note that VP310 compensates for any frequency offsets before qpsk demodulation. hence a frequency offset will not necessarily lead to a performance loss. performance loss will occur only if part of the si gnal is cut off by the saw or base-band filter, due to this frequency offset. this w ill happen only if the symbol rate is close to maximum supported by that filter. in such an event it is recommended that front-end be re-tuned to neutralise this error before the saw filter. it is then necessary for the VP310 to re-acquire the signal. the VP310 can generate control signals to enable full control of the dish and lnb. the chip implements the signals needed for the full diseqc v1.1 specification. this includes high/low band selection, polarisation and dish position. the microprocessor interface is via the primary i 2 c bus. the tuner control from the VP310 is via either i 2 c bus or 3-wire bus, recreated on the general purpose port (gpp). 1.5.1 known symbol rate and code rate mode in this mode, the symbol rate in mbaud and viterbi code rate are the only values needed to start the VP310 searching for the signal. the cdc module maps the high level parameters into the various low level register settings needed to acquire and track the signal. the low level registers may be read and directly modified to suit very specific requirements. however, this is not recommended.
VP310 preliminary data 13 1.5.2 symbol rate and code rate search mode where the symbol rate and/or the viterbi code rate are unknown, the VP310 can be programmed to search for qpsk/bpsk signals. the user should define the range(s) over which the search is required. the VP310 w ill then locate and track any signal detected. failure to find a qpsk signal specified frequency and specified symbol rate ranges w ill be indicated by interrupts. vp 310 will carry on searching these ranges after issuing these interrupts. when the VP310 has locked onto a signal, the symbol rate in mbaud may be read from the monitor registers. the viterbi code rate may be read from the fec_status register. this search facility is primarily for the initial installation of a set top box. 1.6 applications information 1.6.1 if conversion the VP310 has been designed for maximum flexib ility in the satellite application and many options are available. the diagram shown below employs a single conversion system with an if of 480mhz. the saw filter is selected for the maximum data rate expected and a saw resonator is used with the i/q down converter to mix the input down to baseband i and q channels for the VP310 to digitise. the fixed sampling frequency of the VP310 is selected to be either 90mhz or 60 mhz depending on the maximum symbol rate the application must work with. the sample rate must be greater than or equal to twice the symbol rate. for a table showing saw bandwidth versus symbol rate. tuner sl2017 i/q down- converter sl1720 channel decoder VP310 synthesiser sp5769 saw resonator saw filter i2c bus control agc control transport stream o/p i2c control i i/p q i/p rf i/p agc control tank agc amp i/p filter figure 11. single conversion system diagram.
VP310 preliminary data 14 1.6.2 direct conversion figure 12 below shows a direct conversion system that mixes the l-band input to the tuner directly down to i and q baseband channels at zero intermediate frequency. the rf agc amp and tracking filter provide the required tuner noise figure and limit the total power reaching the sl1925. these elements also give isolation between the sl1925 local oscillator and the l-band tuner input. this is an important factor since both signals are at the same frequency. the baseband filter is an anti-alias filter. this replaces the filtering normally carried out with a saw filter in conventional single conversion tuners. it is important to note that all the channel filtering needed to isolate low baud rate signals is contained within the VP310. the low pass filter before VP310 is designed not to filter channels, but to minimise any aliasing due to sampling. to illustrate this, let the sampling frequency be 90 mhz and the maximum symbol rate be 45 mbaud. the bandwidth of the 45 mbaud qpsk signal, with 0.35 roll-off, is about 60 mhz. if the channel has been mapped precisely to base-band, the pass-band of the low pass filter should extend up to 30 mhz. however, it is preferable to make this bandwidth larger by about 5 mhz, partly to reduce the in-band phase distortion introduced by the filter and partly to reduce the loss of signal due to lnb offset. the filter must attenuate signals beyond 60 mhz by about 30 db, as these signal w ill alias to the useful frequency r ange with 90 mhz sampling. although the system is designed for 45 mbaud, if the actual symbol rate is much lower, say 1 mbaud, then VP310 w ill automatically intr oduce all the digital filtering needed to isolate the 1 mbaud signal. direct conversion tuner sl1925 low pass filter channel decoder VP310 synthesiser sp5655/ sp5769 i2c bus control transport stream o/p i2c control i i/p q i/p rf i/p agc control tank agc amp sl1914 i q figure 12. direct conversion system diagram.
VP310 preliminary data 15 2. VP310 software control this section describes the sequences of register operations needed to acquire dvb and dss channels with known or unknown parameters. communication with the VP310 is via a standard i2c bus and the first byte following the chip address, in write mode, is the register address (radd). the register map is organised to group important read registers at the lowest addresses, then the main control write registers in the next block of addresses. the first register to be written must be the configuration register, which has been placed at the highest register address, because it is only written once during the initialisation sequence. the config register can only be reset by the hardware reset. the VP310 is held in a power saving mode following the hardware reset. after a hardware reset, the VP310 must be taken out of the power save mode by writing a one to the msb of the config register. when VP310 is not being used it can be put back into the power save mode by writing a zero to the msb of config. 2.1 initialisation sequence VP310 w ill be in the power save mode after a hardware reset. the first comm and to be written must be to the configuration register at address 127. after loading this register, wait 150s before writing to the reset register. during this wait, the tuner can programmed to the required channel frequency via the general purpose port (register 20). next write 128 to the reset register (21) to reset the VP310 state machine and all parameter registers to the default settings. the default settings of the VP310 assumes a gain control amplifier with a negative gain vs voltage slope, i.e. the gain increases with decreasing voltage. however, if this slope is positive, the polarity of the agc control signal can be inverted by programming 1 to bit b0 of the agc_ctrl register, i.e. by changing the default agc_ctrl setting from 38 to 39. it is best to do this immediately after writing 128 to the reset register. then the agc loop can settle whilst the other registers of VP310 are programmed. note that the initial value, minimum value and the maximum value of the agc control voltage can also be programmed using the corresponding VP310 registers. after this, the lnb controls are defined, in register (22) diseqc_mode. the signal parameters should then be written to the VP310. the symbol rate (registers 23 & 25 sym_rate) may be specified within 2% of the required value, absolute precision is not required to achieve successful lock and tracking. if the symbol rate is unknown, a search mode is available.
VP310 preliminary data 16 selecting the correct bit of register (25) vit_mode, if known, programs the convolutional code rate. if the code rate is unknown, some or all of the bits of vit_mode may be set to force the VP310 to search for the code rate. finally, the VP310 is given a go command, register (27) go = 1, to release the state machine and to start the signal acquisition sequence. this is summarised as an example in the following flow diagram.
VP310 preliminary data 17 enable VP310 : pro g ram config re g 127 = 136 (88hex) pro g ram tuner via gpp in 'pass throu g h mode' open port with re g 20 = 64 (40hex) send tuner data via i2c bus (5 bytes). close port with re g 20 = 0 reset VP310 to default re g ister settin g s re g 21 = 128 (80hex) set agc_sl (if required) initialise re g isters: re g 49 = 50 (32hex); re g 86 = 20 (14hex); re g 87 = 18 (12hex); re g 88 = 2; re g 89 = 1; re g 90 = 0; re g 91 = 0; re g 92 = 0; re g 93 = 0. diseqc mode e g horizontal with 22khz on: re g 22 = 65 (41hex) si g nal input - symbol rate e g 27.5 mbaud: re g 23 = 27 (1bhex) default state re g 24 = 128 (80hex) default state viterbi code rate e g v_iq swap not set, cr = 3/4: re g 25 = 4 (4hex) qpsk control e g dvb : roll-off = 0.35: re g 26 = 0 default state go release reset state to start si g nal capture re g 27 = 1 figure 13. initialisation sequence in dvb mode.
VP310 preliminary data 18 2.2 spectral inversion spectral inversion of the qpsk signal can be caused by the transmitter or the receiver front-end. in the latter case, this could happen due to the way i-q conversion is carried out or because the i and q wires are swapped between the i-q converter and the VP310. if spectral inversion is caused by the receiver front-end, then this must be removed by swapping i and q (within VP310) before qpsk demodulation, by setting q_iq_sp bit b6 of qpsk_ctrl register (26) to 1. if no spectral inversion is caused by the receiver front-end design, then bit b6 of qpsk_ctrl must always be held at zero. if the transmitted signal is known to be spectrally inverted, then v_iq_sp bit b6 of the vit_mode register (25) must be set to 1. then i and q are swapped after qpsk demodulation. if the spectral inversion status of the transmitted signal is not known, then after qpsk has locked (i.e. qpsk_ct_lock = 1), the software must try to achieve fec lock with the bit b6 of vit_mode register first at zero and then at one. 2.3 simple channel change sequence if the VP310 is running, to change channel keeping the same signal conditions, it is only necessary to change the tuner data and possibly the diseqc data. no reset is necessary. program tuner via gpp in 'pass through mode' open port with reg 20 = 64 (40hex) send tuner data via i2c bus (5 bytes). close port with reg 20 = 0 diseqc mode eg vertical with 22khz on: reg 22 = 1 (01hex) go re-acquire signal reg 27 = 1 figure 14. simple channel change sequence.
VP310 preliminary data 19 2.4 channel change sequence with a new symbol rate if the VP310 is running, to change channel and symbol rate but not viterbi coding rate, change the tuner data and possibly the diseqc data and symbol rate. no reset is necessary. program tuner via gpp in 'pass through mode' open port with reg 20 = 64 (40hex) send tuner data via i2c bus (5 bytes). close port with reg 20 = 0 diseqc mode eg horizontal with 22khz on: reg 22 = 65 (41hex) signal input - symbol rate eg 22.0 mbaud : reg 23 = 22 (16hex) reg 24 = 0 viterbi code rate eg v_iq swap not set, cr = 5/6: reg 25 = 8 (8hex) go re-acquire signal reg 27 = 1 figure 15. channel change sequence with new symbol rate, dvb mode.
VP310 preliminary data 20 2.5 channel change sequence with search mode if the signal parameters are unknown, it is possible to instruct the VP310 to find a digital signal and report the parameters found. registers 24 and 25 are programmed with the expected range(s) and the search mode bit sym_rate[b15] is set high. a code rate search is forced by programming more than one bit in vit_mode (26) register. note: code rate 6/7 is not searched for dvb mode. if a signal with the specified symbol rate range (or ranges) is not found in the frequency range searched, a qpsk baud end interrupt (bit b6, qpsk_int_l (2)) is issued. program tuner via gpp in 'pass through mode' open port with reg 20 = 64 (40hex) send tuner data via i2c bus (5 bytes). close port with reg 20 = 0 diseqc mode eg horizontal with 22khz on: reg 22 = 65 (41hex) signal input - search mode eg for sys_clk=60mhz and 30 to 20 mbaud range: reg 23 = 136 (88hex) reg 24 = 0 viterbi code rate search eg v_iq swap not set: reg 25 = 47 (2fhex) go re-acquire signal reg 27 = 1 figure 16. channel change sequence with search mode, dvb mode.
VP310 preliminary data 21 when the VP310 qpsk section has locked to the signal, this is indicated in register (6) by qpsk_stat h[b0] = 1. the symbol rate found can be read from registers (123 C 124) monitor, provided the register (103) mon_ctrl = 3. the tolerance of the result is 0.25%. the 14 msbs of this result (discarding two lsbs) may be written as the 14 lsbs of the 16-bit register pair (23 and 24) sym_rate in the non-search mode for re-acquisition of the same channel. the fec is locked to the signal, when the byte align lock in fec_status[b2] = 1. then the code rate found can be read from fec_status[b6-4], see register 6 for details. program monitor to read symbol rate mon_ctrl reg 103 = 3 read symbol rate from monitor registers 123 & 124. symbol rate = monitor_h/4 + monitor_l/1024 mbaud eg if monitor_h = 27 and monitor_l = 136 then symbol rate = 27.53125 mbaud ie 27.5 mbaud 0.25% read code rate from fec_status[b6-4] register 6. eg if fec_status = 2c hex signal is locked and the code rate = 3/4 figure 17. results of symbol rate and code rate search, dvb or dss mode.
VP310 preliminary data 22 2.6 dss mode of acquisition this mode is very similar to the dvb mode, except that the symbol rate is fixed at 20 mbaud. two code rates are used: dss-a uses 2/3 or dss-b uses 6/7. these are programmed in the register (127) config. if the code rate is unknown, program both dss-a and dss-b to force the VP310 to do a code rate search. after changing the config register, a delay of 150s should be enforced before programming the reset register. the tuner may be programmed via the gpp during this delay period. since both symbol rate and code rate are defined by programming the config register, the contents of registers (23-24) sym_rate and register (25) vit_mode are ignored in dss mode. enable VP310 : program config eg dss-a reg 127 = 166 (a8hex) program tuner via gpp in 'pass through mode' open port with reg 20 = 64 (40hex) send tuner data via i2c bus (5 bytes). close port with reg 20 = 0 reset VP310 to default register settings reg 21 = 128 (80hex) set agc_sl (if required) initialise registers: reg 25 = 16 (10hex); reg 49 = 50 (32 hex) ; reg 50 = 20 (14hex); reg 86 = 20 (14hex); reg 87 = 18 (12hex); reg 88 = 2; reg 89 = 1; reg 90 = 0; reg 91 = 0; reg 92 = 0; reg 93 = 0. diseqc mode eg horizontal with 22khz on: reg 22 = 65 (41hex) go re-acquire signal reg 27 = 1 figure 18. initialisation sequence in dss mode.
VP310 preliminary data 23 2.7 signal and performance monitors the lnb error frequency can be obtained from lnb_freq registers (7 C 8). any lnb error may be removed by offsetting the lnb frequency and re-tuning the tuner by the indicated amount. however, note that VP310 compensates for this frequency error before qpsk demodulation. hence it is not necessary to re-tune the front-end unless this lnb error causes a significant amount of signal energy to be lost due to anti-alias filtering. the tuner rf signal level indication can be obtained from agc h and agc m registers (108 C 109). VP310 input signal level indication can be obtained from sig_lev register (19). an indication of signal to noise ratio (snr) can be obtained from m_snr registers (9 C 10) where a formula is given. this measurement is only intended as a guide to the snr of the channel being received. it should not be taken as the absolute value of snr. qpsk output bit error rate is available by dividing the reading from vit_errcnt registers (11 C 13) by the reading from vit_errper registers (83 C 85). viterbi output bit error rate is available by reading rs_bercnt registers (14 C 16). two readings are taken with a known time interval separating them. the first reading resets the counter at the start of the time period, so it is ignored. the reed solomon uncorrected block error count can be found from rs_ubc registers (17 C 18). this reading is related to the cycle slip performance of the tuner. the measurement technique is similar to that for the viterbi bit error rate above, two readings being taken over a defined time period. in this case the period will usually be very l ong, say 24 hours, to accumulate a reasonable count.
VP310 preliminary data 24 3. VP310 register map radd is a virtual register with no address containing the address of the register to be accessed. it is written immediately after the i2c write address. name adr b7 b6 b5 b4 b3 b2 b1 b0 def hex radd n/a iai ad6 ad5 ad4 ad3 ad2 ad1 ad0 - 3.1 write / read register map name adr b7 b6 b5 b4 b3 b2 b1 b0 def hex gpp_ctrl 20 reserved i2c_pas gpp_dir[2:0] gpp_pin[2:0] 20 reset 21 fr _310 pr_310 fr_qp pr_qp fr_vit pr_vit pr_ba pr_ds 00 diseqc_mode 22 reserved hv diseqc instruction length 22khz mode 00 sym_rate h 23 search reserved sym_rate[13:8] in mbaud (high byte) 1b sym_rate l 24 sym_rate[7:0] in mbaud (low byte) 80 vit_mode 25 reserved v_iq_sp cr 7/8 cr 6/7 cr 5/6 cr 3/4 cr 2/3 cr 1/2 44 qpsk_ctrl 26 reserved q_iq_sp reserved reserved reserved afc_m reserved ro ll_20 00 go 27 reserved go 00 ie_qpsk h 28 ie_qpsk[23:16] interrupt enable qpsk (high byte) 00 ie_qpsk m 29 ie_qpsk[15:8] interrupt enable qpsk (middle byte) 00 ie_qpsk l 30 ie_qpsk [7:0] interrupt enable qpsk (low byte) 00 ie_fec 31 ie_fec[7:0] interrupt enable fec 00 qpsk_stat_en 32 qpsk_stat_en[7:0] enable various qpsk outputs on status pin 00 fec_stat_en 33 fec_stat_en[3:0] enable various fec outputs on status pin 04 sys_clk 34 sys_clk[7:0] - system clock frequency x2 in mhz 00 diseqc_ratio 35 diseqc_ratio[7:0] 00 diseqc_instr 36 diseqc instruction [7:0] 00 fr_lim 37 reserved fr_lim[6:0] - freq. limit in mhz 30 fr_off 38 fr_off[7:0] - freq. offset in mhz 00 agc_ctrl 39 reserved reserved agc_sd[1:0] agc_bw[2:0] agc_sl 26 agc_ref 41 agc_ref[7:0] agc reference level 67 op_ctrl 96 reserved bkeriv mclkiv en_tei bso ba_lk[2:0] 33 mon_ctrl 103 mon_ctrl[7:0] monitor control 00 config 127 310_en dss_b dss_a bpsk p ll_factor[1:0] crys15 adcext 08
VP310 preliminary data 25 3.2 read only register map writing to these registers will have no effect. name adr b7 b6 b5 b4 b3 b2 b1 b0 def hex qpsk_int h 00 qpsk_int[23:16] interrupt qpsk (high byte) 00 qpsk_int m 01 qpsk_int [15:8] interrupt qpsk (middle byte) 00 qpsk_int l 02 qpsk_int [7:0] interrupt qpsk (low byte) 00 fec_int 03 fec_int[7:0] interrupt fec 00 qpsk_stat h 04 qpsk status[15:8] (high byte) 00 qpsk_stat l 05 qpsk status[7:0] (low byte) 00 fec_status 06 fec status[7:0] 00 lnb_freq h 07 lnb_freq[15:8] measured lnb frequency error (high byte) 00 lnb_freq l 08 lnb_freq [7:0] measured lnb frequency error (low byte) 00 m_snr h 09 reserved m_snr[14:8] measured snr (high byte) 00 m_snr l 10 m_snr [7:0] measured snr (low byte) 00 vit_errcnt h 11 vit_errcnt[23:16] - viterbi error count (high byte) 00 vit_errcnt m 12 vit_errcnt [15:8] - viterbi error count (middle byte) 00 vit_errcnt l 13 vit_errcnt [7:0] - viterbi error count (low byte) 00 rs_bercnt h 14 rs_bercnt [23:16] - reed solomon bit errors corrected (high byte) 00 rs_bercnt m 15 rs_bercnt[15:8] - reed solomon bit errors corrected (middle byte) 00 rs_bercnt l 16 rs_bercnt[7:0] - reed solomon bit errors corrected (low byte) 00 rs_ubc h 17 rs_ubc [15:8] - reed solomon uncorrected block errors (high byte) 00 rs_ubc l 18 rs_ubc[7:0] - reed solomon uncorrected block errors (low byte) 00 sig_level 19 sig_level[11:4] - signal level at vp 310 input 00 agc h 108 agc[23:16] - front end agc (high byte) 00 agc m 109 agc[15:8] - front end agc (middle byte) 00 agc l 110 agc[7:0] - front end agc (low byte) 00 freq_err1 h 111 freq_err1[23:16] input frequency error course (high byte) 00 freq_err1 m 112 freq_err1[15:8] input frequency error course (middle byte) 00 freq_err1 l 113 freq_err1[7:0] input frequency error course (low byte) 00 freq_err2 h 114 freq_err2[15:8] input frequency error fine (high byte) 00 freq_err2 l 115 freq_err2[7:0] input frequency error fine (low byte) 00 sym_rat_op h 116 sym_rat_op[15:8] symbol rate output (high byte) 00 sym_rat_op l 117 sym_rat_op [7:0] symbol rate output (low byte) 00 monitor h 123 monitor[15:8] monitor (high byte) 00 monitor l 124 monitor[7:0] monitor (low byte) 00
VP310 preliminary data 26 4. electrical characteristics 4.1 recommended operating conditions parameter symbol min. typ. max. units power supply voltage vdd 3.0 3.3 3.6 v power supply current idd tbd ma input clock frequency 1 xti 9.99 16.00 mhz scl clock frequency fscl 450 khz ambient operating temperature 0 70 c table 1. recommended operating conditions. note 1. when not using a crystal, xti may be driven from an external source over the frequency range shown. 4.2 absolute maximum ratings parameter symbol min. max. unit power supply vdd -0.3 +3.6 v voltage on input pins (5 v rated) vi -0.3 5.5 v voltage on input pins (3.3v rated) vi -0.3 vdd + 0.3 v voltage on output pins (5v rated) vo -0.3 5.5 v voltage on output pins (3.3v rated) vo -0.3 vdd + 0.3 v storage temperature tstg -55 150 oc operating ambient temperature top 0 70 oc junction temperature tj 125 oc table 2. maximum operating conditions. note: stresses exceeding these listed under absolute maximum ratings may induce failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functi onality at or above these conditions is not implied.
VP310 preliminary data 27 4.3 crystal specification parallel resonant fundamental frequency (preferred) 9.99 to 16.00mhz. tolerance over operating temperature range 25ppm. tolerance overall 50ppm. nominal load capacitance 30pf. equivalent series resistance <35 w 33pf 33pf xti xto gnd figure 19. crystal oscillator circuit. note: the crystal frequency should be chosen to ensure that the system clock would marginally exceed the maximum symbol rate required. 4.4 dc electrical characteristics parameter conditions / pin symbol min. typ. max. unit operating voltage vdd 3.0 3.3 3.6 v average power supply current idd tbd ma average supply current stand-by mode tbd m a output levels voh tri-state push pull 1 ma drive current. iin, qin, clkout, mdo, moval, mostrt, mclk, bkerrb, disecq, status voh 0.80vdd 0.92vdd v output levels vol tri-state push pull 1 ma drive current, pins as voh. vol 0.2 0.4 v output level open drain 4 ma drive current. 6 ma drive current. agc, sda, irqb, gpp<2:0> 0.4 0.6 v v open drain output max. voltage 5.5 v input levels vih cmos 3.3v input vih 0.8vdd 3.6 v input levels vih cmos 5.0v input vih 0.8vdd 5.5 v input levels vil cmos vil 0.2vdd v input leakage current vin = 0 and vdd 10 m a table 3. dc electrical characteristics.
VP310 preliminary data 28 4.5 numerical listing of pin-out pin function pin function pin function pin function 1 vss 21 pllvdd 41 vss 61 mdo[1] 2 vdd 22 pllgnd 42 vdd 62 vdd 3 iin[1] 23 pll1 43 agc 63 mdo[2] 4 iin[0] 24 adcfgnd 44 gpp[0] (scl2) 64 mdo[3] 5 qin[5] 25 adcfvdd 45 gpp[1] (sda2) 65 mdo[4] 6 qin[4] 26 vrt 46 gpp[2] 66 mdo[5] 7 qin[3] 27 iref 47 diseqc[1] 67 vdd 8 qin[2] 28 isingp 48 diseqc[0] 68 mdo[6] 9 vdd 29 comp 49 reset 69 mdo[7] 10 vss 30 adcdvdd 50 vdd 70 vss 11 qin[1] 31 adcdgnd 51 vss 71 mdoen 12 qin[0] 32 vrm 52 status 72 moval 13 vdd 33 qsingp 53 scl 73 vdd 14 clkin 34 qref 54 sda 74 vss 15 vss 35 vrb 55 vdd 75 bkerr 16 clkout 36 adcagnd 56 vss 76 mostrt 17 vdd 37 adcavdd 57 irq 77 iin[5] 18 xti 38 rref 58 mclk 78 iin[4] 19 xto 39 test1 59 mdo[0] 79 iin[3] 20 vss 40 test2 60 vss 80 iin[2] table 4. numerical listing of pin-out.
VP310 preliminary data 29 5. appendix 1: application schematic clkin 14 clkout 16 pllvdd 21 pllgnd 22 pll1 23 adcfgnd 24 adcfvdd 25 vrt 26 iref 27 isingp 28 comp 29 adcdvdd 30 adcdgnd 31 vrm 32 qsingp 33 qref 34 vrb 35 adcagnd 36 adcavdd 37 rref 38 test1 39 test2 40 agc 43 gpp0/scl out 44 gpp1/sda out 45 gpp2 46 disecq1/h/v 47 disecq0/22khz 48 resetb 49 status 52 scl 53 sda 54 irqb 57 mclk 58 mdo0 59 mdo1 61 mdo2 63 mdo3 64 mdo4 65 mdo5 66 mdo6 68 mdo7 69 mdoenb 71 moval 72 bkerrb 75 mostrt 76 iin5 77 iin4 78 iin3 79 iin2 80 iin1 3 iin0 4 qin5 5 qin4 6 qin3 7 qin2 8 qin1 11 qin0 12 xtib 18 xto 19 ic1 VP310 xl1 10mhz c1 33pf c2 33pf c3 100nf c4 100nf c5 100nf c6 100nf c7 100nf c8 100nf c9 100nf c10 100nf c11 100nf c12 100nf vdd c13 33n iflt qflt agc c14 100n + c34 22u vdd l1 1u c15 100n l2 1u l3 1u c16 100n c17 100n c18 100n c19 470n c20 470n c21 100n c22 100n c23 100n c24 100n c25 100n r1 1k2 r2 100 r3 390 +5v c26 1n r4 1k5 r5 10k r6 10k scl2 sda2 gpp2 r7 1k0 r8 1k0 r9 4k7 c27 100n c28 1n +5v disecq1 disecq0 +5v r10 4k7 r11 4k7 r12 4k7 r13 100 r14 100 c29 100p c30 100p c31 100n c32 1n scl1 sda1 resetb status irqb r15 4k7 mpeg c33 100n l4 1u vdd figure 20. application schematic.

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